Scope
NiFpga_AnalogDemultiplexerV2_NI5771.h
1 /*
2  * Generated with the FPGA Interface C API Generator 12.0.0
3  * for NI-RIO 12.0.0 or later.
4  */
5 
6 #ifndef __NiFpga_AnalogDemultiplexerV2_NI5771_h__
7 #define __NiFpga_AnalogDemultiplexerV2_NI5771_h__
8 
9 #ifndef NiFpga_Version
10  #define NiFpga_Version 1200
11 #endif
12 
13 #include "NiFpga.h"
14 
22 #define NiFpga_AnalogDemultiplexerV2_NI5771_Bitfile "NiFpga_AnalogDemultiplexerV2_NI5771.lvbitx"
23 
27 static const char* const NiFpga_AnalogDemultiplexerV2_NI5771_Signature = "9C64626794B6859E042752A0A66A1B22";
28 
29 typedef enum
30 {
31  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_Acquiring = 0x36,
32  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_Configured = 0x6E,
33  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_IOModuleAIOverRange = 0x8000001A,
34  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_InterloopFIFOOverflow = 0x8000000A,
35  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_InterloopFIFOtimeout = 0x32,
36  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_PLLLocked = 0x66,
37  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_ToHostA1FIFOOverflow = 0x26,
38  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_ToHostA2FIFOOverflow = 0x22,
39  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_UserCommandIdle = 0x56,
40  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool_UserError = 0x6A,
41 } NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorBool;
42 
43 typedef enum
44 {
45  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorU8_UserCommandStatus = 0x5A,
46 } NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorU8;
47 
48 typedef enum
49 {
50  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorU32_PixelcounterA1 = 0x2C,
51  NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorU32_PixelcounterA2 = 0x28,
52 } NiFpga_AnalogDemultiplexerV2_NI5771_IndicatorU32;
53 
54 typedef enum
55 {
56  NiFpga_AnalogDemultiplexerV2_NI5771_ControlBool_Acquire = 0x3E,
57  NiFpga_AnalogDemultiplexerV2_NI5771_ControlBool_Acquirecontinuously = 0x46,
58  NiFpga_AnalogDemultiplexerV2_NI5771_ControlBool_ClearInterloopFIFO = 0x1E,
59  NiFpga_AnalogDemultiplexerV2_NI5771_ControlBool_UserCommandCommit = 0x4E,
60  NiFpga_AnalogDemultiplexerV2_NI5771_ControlBool_Waitfortrigger = 0x3A,
61 } NiFpga_AnalogDemultiplexerV2_NI5771_ControlBool;
62 
63 typedef enum
64 {
65  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8_BaselineU8Ch1 = 0x80000012,
66  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8_BaselineU8Ch2 = 0x8000000E,
67  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8_CutoffU8Ch1 = 0x80000006,
68  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8_CutoffU8Ch2 = 0x80000002,
69  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8_UserCommand = 0x52,
70  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8_UserData1 = 0x62,
71 } NiFpga_AnalogDemultiplexerV2_NI5771_ControlU8;
72 
73 typedef enum
74 {
75  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU16_Samplesperpixel = 0x80000016,
76  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU16_UserData0 = 0x5E,
77 } NiFpga_AnalogDemultiplexerV2_NI5771_ControlU16;
78 
79 typedef enum
80 {
81  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU32_RequestedpixelsA1 = 0x48,
82  NiFpga_AnalogDemultiplexerV2_NI5771_ControlU32_RequestedpixelsA2 = 0x40,
83 } NiFpga_AnalogDemultiplexerV2_NI5771_ControlU32;
84 
85 typedef enum
86 {
87  NiFpga_AnalogDemultiplexerV2_NI5771_TargetToHostFifoU64_ToHostA1FIFO = 1,
88  NiFpga_AnalogDemultiplexerV2_NI5771_TargetToHostFifoU64_ToHostA2FIFO = 0,
89 } NiFpga_AnalogDemultiplexerV2_NI5771_TargetToHostFifoU64;
90 
91 #endif