Scope
NiFpga_DigitalDemultiplexerV3.h
1 /*
2  * Generated with the FPGA Interface C API Generator 12.0.0
3  * for NI-RIO 12.0.0 or later.
4  */
5 
6 #ifndef __NiFpga_DigitalDemultiplexerV3_h__
7 #define __NiFpga_DigitalDemultiplexerV3_h__
8 
9 #ifndef NiFpga_Version
10  #define NiFpga_Version 1200
11 #endif
12 
13 #include "NiFpga.h"
14 
22 #define NiFpga_DigitalDemultiplexerV3_Bitfile "NiFpga_DigitalDemultiplexerV3.lvbitx"
23 
27 static const char* const NiFpga_DigitalDemultiplexerV3_Signature = "9DF944060C23FE50E0AF795E74F2DFAC";
28 
29 typedef enum
30 {
31  NiFpga_DigitalDemultiplexerV3_IndicatorBool_Acquiring = 0x22,
32  NiFpga_DigitalDemultiplexerV3_IndicatorBool_InterloopFIFOoverflow = 0x80000066,
33  NiFpga_DigitalDemultiplexerV3_IndicatorBool_InterloopFIFOtimeout = 0x3E,
34  NiFpga_DigitalDemultiplexerV3_IndicatorBool_Onboard_Clock_Ready = 0x56,
35  NiFpga_DigitalDemultiplexerV3_IndicatorBool_ToHostFIFOOverflowA1Ch1 = 0x1E,
36  NiFpga_DigitalDemultiplexerV3_IndicatorBool_ToHostFIFOOverflowA1Ch2 = 0x12,
37  NiFpga_DigitalDemultiplexerV3_IndicatorBool_ToHostFIFOOverflowA2Ch1 = 0xE,
38  NiFpga_DigitalDemultiplexerV3_IndicatorBool_ToHostFIFOOverflowA2Ch2 = 0xA,
39  NiFpga_DigitalDemultiplexerV3_IndicatorBool_Xpoint_Switch_Ready = 0x42,
40 } NiFpga_DigitalDemultiplexerV3_IndicatorBool;
41 
42 typedef enum
43 {
44  NiFpga_DigitalDemultiplexerV3_IndicatorU16_LaserpulsesperpixelA1 = 0x6,
45 } NiFpga_DigitalDemultiplexerV3_IndicatorU16;
46 
47 typedef enum
48 {
49  NiFpga_DigitalDemultiplexerV3_ControlBool_Acq_Reset = 0x8000006A,
50  NiFpga_DigitalDemultiplexerV3_ControlBool_Acquire = 0x3A,
51  NiFpga_DigitalDemultiplexerV3_ControlBool_Acquirecontinuously = 0x2A,
52  NiFpga_DigitalDemultiplexerV3_ControlBool_ClearInterloopFIFO = 0x32,
53  NiFpga_DigitalDemultiplexerV3_ControlBool_Commit = 0x2,
54  NiFpga_DigitalDemultiplexerV3_ControlBool_Countmode = 0x8000005A,
55  NiFpga_DigitalDemultiplexerV3_ControlBool_Onboard_Clock_Write = 0x4E,
56  NiFpga_DigitalDemultiplexerV3_ControlBool_Waitfortrigger = 0x26,
57  NiFpga_DigitalDemultiplexerV3_ControlBool_Xpoint_Switch_Write = 0x46,
58 } NiFpga_DigitalDemultiplexerV3_ControlBool;
59 
60 typedef enum
61 {
62  NiFpga_DigitalDemultiplexerV3_ControlU8_ClockSource = 0x4A,
63 } NiFpga_DigitalDemultiplexerV3_ControlU8;
64 
65 typedef enum
66 {
67  NiFpga_DigitalDemultiplexerV3_ControlU16_Onboard_Clock_Write_Data = 0x52,
68  NiFpga_DigitalDemultiplexerV3_ControlU16_SamplesperpixelA1 = 0x36,
69  NiFpga_DigitalDemultiplexerV3_ControlU16_SamplesperpixelA2 = 0x1A,
70  NiFpga_DigitalDemultiplexerV3_ControlU16_SamplesperpixelAcqA1 = 0x80000062,
71  NiFpga_DigitalDemultiplexerV3_ControlU16_SamplesperpixelAcqA2 = 0x8000005E,
72 } NiFpga_DigitalDemultiplexerV3_ControlU16;
73 
74 typedef enum
75 {
76  NiFpga_DigitalDemultiplexerV3_ControlU32_RequestedpixelsA1 = 0x2C,
77  NiFpga_DigitalDemultiplexerV3_ControlU32_RequestedpixelsA2 = 0x14,
78 } NiFpga_DigitalDemultiplexerV3_ControlU32;
79 
80 typedef enum
81 {
82  NiFpga_DigitalDemultiplexerV3_TargetToHostFifoU16_ToHostArea1Ch1FIFO = 3,
83  NiFpga_DigitalDemultiplexerV3_TargetToHostFifoU16_ToHostArea1Ch2FIFO = 2,
84  NiFpga_DigitalDemultiplexerV3_TargetToHostFifoU16_ToHostArea2Ch1FIFO = 1,
85  NiFpga_DigitalDemultiplexerV3_TargetToHostFifoU16_ToHostArea2Ch2FIFO = 0,
86 } NiFpga_DigitalDemultiplexerV3_TargetToHostFifoU16;
87 
88 #endif