Example config for a one-area FPGA/DAQmx system using one NI-6259 card and a NI-7962R FPGA with NI FlexRIO 6587 adapter module (photon counting).

In this configuration the concept is to output scanner/fast z/Pockels signals from a regular 6259 card.

PMT signals are pulse amplified (by e.g. Alphalas BVG-100 amplifier) and converted to LVDS pulses (by e.g. PulseResearchLab comparator and logic level converter). The LVDS signals are then read in with a very fast (> 1GHz) LVDS digital input adapter card (NI 6587) on an FPGA (e.g. 7962R). Depending on your imaging conditions this can give superior signal-to-noise performance compared to regular analog integration. But be aware that the apparent signal levels are very low! Having a pixel time of 6 µs gives you 480 laser pulses per pixel. Ideally for this configuration you have 0-1 photons (better: photoelectrons) per laser pulse. Then your maximum signal level would be 480. Higher photon fluxes still lead to an increase in the apparent signal level, since the photon counter vi on the FPGA counts the "high" samples. For higher photon flux you have several photons per laser pulse, but the signal that reaches the comparator could be a large pulse. This pulse is over the threshold for more samples than a single photon pulse, but the relationship is non-linear (in whatever complex way). Etc..

Copy ScopeDefinesExamples.h (which is in the repository) to ScopeDefines.h by using Windows Explorer (not Visual Studio!). Git ignores ScopeDefines.h so that you can adapt this to your needs without messing up for other people. Now choose the following defines in ScopeDefines.h

• #define SCOPE_NAREAS 1
• #define SCOPE_USE_SIMPLEDAQMX_OUTPUTS
• #define SCOPE_USE_FPGAPHOTONCOUNTER_INPUTS and xyz hardware as you want it e.g. #define SCOPE_USE_NOXYFPUSTAGE and #define SCOPE_USE_GALIL_XYZSTAGE. Then compile your scope.exe.
• Check http://sine.ni.com/nips/cds/view/p/lang/en/nid/14129 for details of the 6259 card.
• Check http://sine.ni.com/nips/cds/view/p/lang/en/nid/208166 for detail of the 7962R FPGA
• Check http://sine.ni.com/nips/cds/view/p/lang/en/nid/209270 for details of the 6587 high-speed digital adapter module

Now to the xml file (remember: you can find all the parameters here in scope::parameters with detailed descriptions!):

<?xml version="1.0" encoding="utf-8"?>
<scope>
    <Date>2013-04-03</Date>
    <Time>10-20-54</Time>
    <Comment></Comment>
    <StartInputsFirst>false</StartInputsFirst>
    <CommonMasterTrigger>/PXI-6259_0/ao/StartTrigger</CommonMasterTrigger>
    <MasterFOVSizeX_um>3000</MasterFOVSizeX_um>
    <MasterFOVSizeY_um>3000</MasterFOVSizeY_um>

Since the FPGA provides a sample clock for the 6259 card (via the PXI_Trig1 PXI chassis line), we have to start the outputs task first. It waits then for its sample clock which will arrive when we now start the FPGA inputs task. Since there is only one area we can leave the ao/StartTrigger of the 6259 as CommonMasterTrigger (it does not matter anyhow).